Area and Power Consumption Trade-off for Sigma-Delta Decimation Filter in Mixed Signal Wearable IC

Area and Power consumption are important design metrics in integrated circuit (IC), in particular in those targeted for wearable devices. Σ-∆ Analog to Digital Converter (ADC) are increasing in popularity in those devices thanks to the low bandwidth of a great number of sensors that permits to increase converter performances by the oversampling and noise shaping techniques. One of the most important part of the Σ-∆ ADC is the decimation filter, usually implemented as a Cascaded Integrator Comb (CIC). The various CIC architectures, in particular the Recursive and Non recursive Polyphase ones, are well known in literature. However, filters on-chip performances are strictly related to the effective implementations. The aim of this paper is to evaluate the two architectures, with different values of the characteristic parameters, optimizing the 180 nm CMOS Standard Cell technology design for a reduced area occupation or power consumption. Results prove that polyphase implementations, differently from theoretical analysis, are generally more power efficient than the recursive one only in a clock gated design, even with a higher area occupation. In addition, an estimation of the power consumption is provided using least squares regression. 1